This disclosure relates to a clock and data recovery (“CDR”) circuit having a phase interpolator producing an output signal with edges that are controlled in phase position so as to fall at a required phase position between two phase signals that are earlier and later than a targeted phase position.
CDR circuits are useful, for example, in decoding high data rate serial data streams transmitted between two digital devices, without the need to transmit a separate clock signal as a timing reference for decoding or synchronizing with the serial data stream. A reference clock is regenerated at the receiving device using a controllable oscillator in a phase locked loop or a controllable delay in a delay locked loop. Feedback controls cause the controllable oscillator or delay to generate a local clock signal that is locked onto a frequency and phase that matches the transitions in the serial data stream. The regenerated clock produced from the data signal is used at the receiver device to synchronize decoding operations with the transmitter clock. Operations are synchronized without the need to couple directly with the transmitter clock signal.
Advantageously, the phase position of the regenerated clock is adjustable more finely than the phase difference between phase subdivisions, by interpolating between the transitions of two phase subdivisions. An output phase signal is adjusted such that transitions in the output phase signal occur at an adjustable time between leading and lagging phase subdivisions.
What is needed are circuits and techniques that optimize and improve phase interpolations devices and techniques.